The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an element isolation region and a method for manufacturing the same.
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements over a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique will be described below.
FIGS. 13 through 15 schematically show steps of forming element isolation regions using a conventional trench isolation technique. FIG. 13 is a plan view of a semiconductor wafer over which a pad layer, a polishing stopper layer and a resist layer are successively deposited. FIG. 13 also shows, for description purposes, a range of exposure of the resist layer formed over the semiconductor wafer. FIGS. 14 and 15 schematically show cross-sectional views taken along a line Bxe2x80x94B of FIG. 13 in different steps.
First, a pad layer 112, a polishing stopper layer 114 and a resist layer R2 are successively deposited over a semiconductor wafer 110. Then, as shown in FIG. 13, the resist layer R2 only in a chip region 120 is exposed.
Next, as shown in FIG. 14(a), the resist layer R2 is developed to form the resist layer R2 into a specified pattern. Then, the polishing stopper layer 114 and the pad layer 112 are removed using the resist layer R2 as a mask.
Then, as shown in FIG. 14(b), the resist layer R2 is removed and then trenches 132 are formed in the semiconductor wafer 110 using the polishing stopper layer 114 as a mask.
Then, as shown in FIG. 15(a), a dielectric layer 152 is formed over the semiconductor wafer 110 in a manner to fill the trenches 132 with the dielectric layer 152.
Next, as shown in FIG. 15(b), the dielectric layer 152 is polished by a chemical-mechanical polishing method (hereafter referred to as a xe2x80x9cCMP methodxe2x80x9d). Through the steps described above, the dielectric layer 152 is embedded in the trenches 132, and thereby trench isolation regions are formed.
In view of preventing the throughput of the exposure step from lowering, the resist layer R2 in the non-chip region 122 is not generally exposed, as shown in FIG. 13. As a result, as shown in FIG. 14(b), after the trenches 132 are formed in the semiconductor wafer 110, a relatively wide convex region 160 is formed in the non-chip region 122 adjacent to the chip region 120. The relatively wide convex region 160 formed in the non-chip region 122 adjacent to the chip region 120 causes the following problems.
As shown in FIG. 15(a), when the dielectric layer 152 is formed over the semiconductor wafer 110, the dielectric layer 152 is thickly deposited over the wide convex region 160. If the dielectric layer 152 is polished while the dielectric layer 152 is thickly deposited in the wide convex region 160, the dielectric layer 152 deposited in the wide convex region 160 remains when the polishing of the dielectric layer 152 deposited over the chip region 120 is completed, as shown in FIG. 15(b). Also, due to the presence of the thick dielectric layer 152 formed in the wide convex region 160, the dielectric layer 152 remains in an area over a convex section 162 adjacent to the wide convex region 160. In other word, the dielectric layer 152 in the chip region 120 remains in an area over the convex section 162 adjacent to the non-chip region 122. When the dielectric layer 152 in the chip region 120 remains in an area over the convex section 162 adjacent to the non-chip region 122, the polishing stopper layer 114 cannot be removed, and a element cannot be formed over the convex section 162.
Furthermore, if the dielectric layer 152 is polished while the dielectric layer 152 is thickly deposited in the wide convex region 160, thinning and dishing phenomenon occur. These phenomenon cause variations in the thickness of the dielectric layer 152.
Because of the reasons described above, when the relatively wide convex region 160 is formed in the non-chip region 122 adjacent to the chip region 120, chips that are formed in outermost areas (areas indicated by crosses (x) in FIG. 13) of the chip region 120 may become bad chips. In other words, the yield of chips formed in the chip region other than the outermost areas is lowered.
It is an object of the present invention to provide semiconductor wafers, a method for processing the same and a method for manufacturing semiconductor devices, which improve the yield of chips formed in a chip region other than outermost areas of the chip region.
(1) In accordance with a first embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, trench isolation regions are formed in the semiconductor wafer, and dummy trench isolation regions are formed in at least a part of the non-chip region of the semiconductor wafer, wherein the dummy trench isolation regions are formed in a region extending by a specified distance into the non-chip region from a boundary between the chip region and the non-chip region.
The xe2x80x9cchip regionxe2x80x9d used here refers to a region in a semiconductor wafer where chips can be formed according to a given pattern, and the xe2x80x9cnon-chip regionxe2x80x9d used here refers to a region in the semiconductor wafer where chips cannot be formed according to the given pattern.
In the method for processing a semiconductor wafer in accordance with the first embodiment, dummy trench isolation regions are formed in at least a part of the non-chip region of the semiconductor wafer. In other words, when trenches are formed in the semiconductor wafer to form trench isolation regions in the semiconductor wafer, dummy trenches are formed in the non-chip region. As a result, when a dielectric layer is filled in the trenches, the dielectric layer is prevented from being thickly deposited in a convex region in the non-chip region. Therefore, after the dielectric layer is polished, the dielectric layer is prevented from remaining in convex sections in the chip region adjacent to the non-chip region by the influence of the dielectric layer deposited over the non-chip region. As a result, the yield of chips to be formed in the chip region adjacent to the non-chip region is increased.
The specified distance may preferably be 1.5 mm or greater. When the specified distance is 1.5 mm or greater, the dielectric layer is prevented from remaining over convex sections in the chip region adjacent to the non-chip region.
More preferably, the specified distance may be between 2 mm and 5 mm. When the specified distance is 2 mm or greater, the dielectric layer can be more securely prevented from remaining over convex sections in the chip region adjacent to the non-chip region. Also, when the specified distance is 5 mm or smaller, the chip region can be more effectively defined over the semiconductor wafer.
(2) In accordance with a second embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, the method comprises step (A) of forming trench isolation regions in the semiconductor wafer, wherein step (A) comprises the steps of:
(a) forming a polishing stopper layer having a specified pattern over the semiconductor wafer;
(b) forming trenches in the chip region and dummy trenches in at least a portion of the non-chip region in the semiconductor wafer using at least the polishing stopper layer as a mask, wherein the dummy trench isolation regions are formed in a region extending by a specified distance into the non-chip region from a boundary between the chip region and the non-chip region;
(c) forming a dielectric layer over the semiconductor wafer and filling the trenches and the dummy trenches with the dielectric layer; and
(d) polishing the insulation layer using the polishing stopper layer as a stopper.
A method for processing a semiconductor wafer in accordance with the second embodiment of the present invention can provide the same effects as those provided by the method for processing a semiconductor wafer in accordance with the first embodiment of the present invention.
The specified distance may preferably be 1.5 mm or greater in step (b). When the specified distance may preferably be 1.5 mm or greater, the dielectric layer is prevented from remaining over convex sections in the chip region adjacent to the non-chip region.
More preferably, the specified distance may be between 2 mm and 5 mm in step (b). When the specified distance is 2 mm or greater, the dielectric layer can be more securely prevented from remaining over convex sections in the chip region adjacent to the non-chip region. Also, when the specified distance is 5 mm or smaller, the chip region can be more effectively defined over the semiconductor wafer.
In accordance with a third embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, the method comprises step (A) of forming trench isolation regions in the semiconductor wafer, wherein step (A) comprises the steps of:
(h) forming a polishing stopper layer over the semiconductor wafer;
(i) forming a resist layer over the polishing stopper layer;
(j) exposing the resist layer in the chip region and at least one specified portion of the non-chip region, wherein the resist layer is exposed in a region extending by a specified distance into the non-chip region from a boundary between the chip region and the non-chip region;
(k) developing the resist layer;
(l) removing the polishing stopper layer in a specified pattern using the resist layer as a mask;
(m) etching the semiconductor wafer using at least the polishing stopper layer as a mask to form trenches in the chip region and dummy trenches in the non-chip region;
(n) forming a dielectric layer over the semiconductor wafer and filling the trenches and the dummy trenches with the dielectric layer; and
(o) polishing the dielectric layer using the polishing stopper layer as a stopper.
A method for processing a semiconductor wafer in accordance with the third embodiment of the present invention can provide the same effects as those provided by the method for processing a semiconductor wafer in accordance with the first embodiment of the present invention.
The specified distance may preferably be 1.5 mm or greater in step (j). When the specified distance may preferably be 1.5 mm or greater, the dielectric layer is prevented from remaining over convex sections in the chip region adjacent to the non-chip region.
More preferably, the specified distance may be between 2 mm and 5 mm in step (j). When the specified distance is 2 mm or greater, the dielectric layer can be more securely prevented from remaining over convex sections in the chip region adjacent to the non-chip region. Also, when the specified distance is 5 mm or smaller, the chip region can be more effectively defined over the semiconductor wafer.
In accordance with another embodiment of the present invention, a semiconductor wafer has a chip region and a non-chip region, wherein the semiconductor wafer comprises dummy trench isolation regions in at least a part of the non-chip region. In one aspect, the dummy trench isolation regions are formed in a region extending by a specified distance into the non-chip region from a boundary between the chip region and the non-chip region.
When semiconductor devices are manufactured using a semiconductor wafer manufactured in accordance with the present invention, the yield of chips to be formed in the chip region adjacent to the non-chip region is increased for the same reasons described above in connection with the methods for processing semiconductor wafers.
In one aspect of the present invention, the specified distance may preferably be 1.5 mm or greater. When the specified distance is 1.5 mm or greater, the dielectric layer is prevented from remaining over convex sections in the chip region adjacent to the non-chip region.
More preferably, the specified distance may be between 2 mm and 5 mm. When the specified distance is 2 mm or greater, the dielectric layer can be more securely prevented from remaining over convex sections in the chip region adjacent to the non-chip region. Also, when the specified distance is 5 mm or smaller, the chip region can be more effectively defined over the semiconductor wafer.
In accordance with still another embodiment of the present invention, a method for manufacturing a semiconductor device includes a method for processing a semiconductor wafer according to any one of claims 1 through 9.
By the method for manufacturing a semiconductor device in accordance with the present invention, the yield of chips to be formed in the chip region adjacent to the non-chip region is increased for the same reasons described above in connection with the methods for processing semiconductor wafers.